Reset circuit

Abstract

PURPOSE: To surely operate the circuit even against a change showing a slow power voltage rising by providing a waveform shaping means and an RC time constant circuit retarding the signal obtained from the means. CONSTITUTION: The time till an output V 1 of an RC time constant circuit 3 reaches a threshold voltage of an inverter Schmitt 4 is retarded according to the time constant when the time constant of the RC time constant circuit is selected longer than the time when the power voltage VCC does not reach its top but arrives in the steady-state soon. When the output V 1 of the RC time constant circuit 3 reaches a threshold voltage, the inverter Schmitt changes the state and the output RESET changes from '1' to '0'. Thus, the initial reset signal for a digital circuit or the like is operated stably by retarding the reset signal by a prescribed time after the power voltage VCC reaches the steady-state and changing the state of the reset signal. COPYRIGHT: (C)1990,JPO&Japio

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Cited By (6)

    Publication numberPublication dateAssigneeTitle
    CN-102480283-AMay 30, 2012快捷半导体(苏州)有限公司, 快捷半导体公司Power-on reset
    JP-2001267980-ASeptember 28, 2001Oki Electric Ind Co Ltd, Techno Collage:Kk, 株式会社テクノコラージュ, 沖電気工業株式会社Contactless signal transmission and reception circuit
    JP-2010109971-AMay 13, 2010Semiconductor Energy Lab Co Ltd, 株式会社半導体エネルギー研究所Reset signal generation circuit and semiconductor device
    JP-4526644-B2August 18, 2010Okiセミコンダクタ株式会社, 株式会社 沖テクノコラージュ非接触の信号送受信回路
    US-2012126864-A1May 24, 2012Tyler Daigle, Julie Lynn StultzPower-on reset
    US-8353460-B2January 15, 2013Semiconductor Energy Laboratory Co., Ltd.Reset signal generation circuit and semiconductor device